Sample-and-hold unit

ABSTRACT

This sample-and-hold unit comprises a capacitor for memorizing voltage samples and a passive compensation circuit, for substantially duplicate said voltage memorization, and adapted to compensate for a residual voltage after a first memorization by feeding back a portion of the duplicate memorized voltage.

BACKGROUND OF THE INVENTION

This invention relates to an improved sample-and-hold unit whereby thediaphony or crosstalk phenomenon between sequentially memorized signalsamples can be reduced.

The sample-and-hold unit according to the invention is particularlyadapted to memorize successive electric voltage samples within a verywide dynamic range of variations such as those produced, for example, bya multiplexer heading a seismic data acquisition chain.

For reasons which will be explained below, in the following description,the sample-and-hold units currently in use do not provide for thesuccessive memorization of two samples without occurrence of interactionthere between. Accordingly, the memorized value of a sample amplitude isnot independent from the memorized value of the amplitude of thepreceding sample. The separating power or capability of asample-and-hold unit is defined as the rate of diaphony betweensuccessive samples. This rate never exceeds -80 dB whereas it would benecessary to obtain a rate of -100 dB for example in seismic acquisitionchains.

A known method for overcoming the performance limitations of thesample-and-hold units presently in use, consists of omitting them andadapting the following part of the acquisition chain by taking intoaccount the fact that the amplitude of the input signal is alwayschanging. The multiplexer output is connected permanently to the sampleamplifier, the amplitude of each sample, varies within the samplingperiod and, consequently, it is required that the gain programcontrolling the variation of the amplifier gain, take this variationinto account so as to anticipate its probable variation. It thus becomesnecessary to measure the signal derivative or the slope of itsrepresenting curve and to make use of a gain selection algorithm wherebysaid gain can be decreased. This algorithm is necessarily more complexthan that usable in an acquisition chain comprising a sample memorizingelement in which only a uniform gain increase is considered. Since saidalgorithm is operational in the form of an assembly of logic cabledelements, it results that the sample amplifier provided with suchassembly is necessarily bulkier and consumes more power. Thesedisadvantages are particularly troublesome when the data acquisitionchain must be housed in a limited space not readily accessible, such asinside a seismic streamer.

SUMMARY OF THE INVENTION

The sample-and-hold unit according to the invention includessample-and-hold means comprising a capacitor for memorizing voltagesamples and means for charging the memorization capacitor with thevoltage to be memorized during the sampling periods and for isolatingthe latter during the holding periods, a second capacitor having a firstterminal connected intermittently to the output of the sample-and-holdmeans and a second terminal connected to ground and means forsubtracting, from the voltage applied to the memorization capacitor, aportion of the voltage applied to the terminals of the second capacitor.More specifically, the invention comprises a passive compensationcircuit comprising the second capacitor, and means to short-circuitintermittently the second capacitor, said passive compensation circuitbeing adapted to reproduce the actual operational characteristics of thememorizing capacitor.

The sample-and-hold unit according to the invention is adapted toreproduce and to compensate for phenomena occuring during the operationof a memorizing capacitor, and permits reducing to a large extent theinteraction between the successively memorized voltages. As aconsequence, the diaphony rate between successive samples substantiallyincreases to reach a value of -100 dB compatible for use in a seismicacquisition chain, and the recourse to a logic gain control system ofhigh performance can be avoided.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the sample-and-hold unit according tothe invention will become apparent from the following description of apreferred embodiment thereof, given with reference to the accompanyingdrawing wherein:

FIG. 1 diagrammatically shows a prior art sample-and-hold unit of aknown type;

FIG. 2 is a graph showing curves of variations, over a period of time,of the input and output voltages of a sample-and-hold unit of a knowntype;

FIG. 3 shows an equivalent circuit to a real capacitor C;

FIG. 4 shows a schematic diagram of the passive compensation deviceaccording to the invention associated with a sample-and-hold unit of aknown type, and

FIG. 5 is a graph showing curves of variation, over a period of time, ofvoltages at various points when using the device of FIG. 4.

DETAILED DISCUSSION OF THE INVENTION

The sample-and-hold unit of a known type, illustrated in FIG. 1,comprises two operational amplifiers A₁ and A₂, arranged in series, theoutput of the first one is connected, through breaker I, preferably ofelectronic type, with the non-inverting input of the second amplifier A₂which is also connected to ground through a capacitor C. The outputimpedance of the first amplifier A₁ is low, whereas the input impedanceof the second is very high. The first amplifier A₁ is an isolatingamplifier with a gain of one, whose output signal reproduces the signalV_(e) applied to its non-inverting input. At instant t₀ where voltageV_(c) to the terminals of the capacitor C is, for example, S₀ (FIG. 2),the electronic breaker I is switched on and the condensor C is rapidlycharged or discharged (sampling period) so as to equalize voltage V_(c)to the voltage V_(e) at instant t₁ where the breaker is switched off.The input impedance of the amplifier A₂ being very high, the voltageV_(c) remains practically constant over a second period called holdingperiod and memorizes the value at instant t₁ of the sample. It isassumed that during the holding period (t₁ -t₂), the input signal V_(e)has rapidly decreased down to a substantially zero value (wide dynamicof range). During the period (t₂ -t₃) where the electronic breaker I isagain switched on (sampling period), the voltage V_(c) decreases downalso to a substantially zero value. However, at instant t₃ where againthe breaker I is switched off, it is observed that the voltage V_(c) andconsequently, the voltage V_(s) at the output of amplifier A₂, insteadof keeping its substantially zero value S' reached at the end of t₂ -t₃period, is subjected to an abrupt variation and takes an effective valueS₂ which is proportional to amplitude S₁ memorized for the precedingsample.

This effect can be explained by the fact that the real capacitor C isequivalent (FIG. 3) to a theoretically leak-free capacitor C₀ connectedin parallel with a branched line comprising a resistor or resistance R₁,and a capacitor of capacitance C₁ connected in series, the latter havinga capitance substantially below that of C₀. When the voltage applied tothe terminals of capacitor C substantially falls to zero (period t₂-t₃), capacitor C₀ is practically short-circuited and capacitor C₁discharges through resistor R₁ with a time constant R₁ C₁ sufficientlyhigh so as to retain a residual charge at instant t₃. When breaker I isagain switched off (instant t₃), capacitor C₁ finally discharges andtransfers to capacitor C₀ the residual charge. The residual chargeappears on the terminals of capacitor C₀ as an error voltage S₂ whichdepends i.e., is proportional, on the charge stored by the capacitorduring the holding period of the preceding sample and, consequently, ofthe charge voltage S₁.

The sample-and-hold unit according to the invention (FIG. 4) comprises,as that illustrated in FIG. 1, an isolating amplifier A₁ with a gain ofone, receiving a signal V_(e) at its non-inverting input E and whoseoutput is connected, through a breaker I₁ preferably of electronic typeto the non-inverting input of high impedance of a differential amplifierA₂. This same input is connected to the ground through a capacitor C formemorizing samples, represented in the Figure for the purpose ofexplaining its operation, by an equivalent circuit consisting of aleak-free capacitor C₀ connected in parallel to a branched lineconsisting of a capacitor C₁ connected in series with a resistor R₁similar to the equivalency shown in FIG. 3.

The device of the invention differs from the prior devices in that itcomprises a passive compensation circuit including three branched linesin parallel, a first one comprising a resistor of resistance R₃connected in series with a capacitor of capacitance C₃, a second oneincluding a capacitor C₂ and a third one an electronic breaker I₃. Thepassive compensation circuit has one of its ends connected to ground andits second end connected to the output of operational amplifier A₂through a breaker I₂ preferably of the electronic type. The second endof the passive compensation circuit is also connected, ahead of thebreaker I₂ to the non-inverting input of a third amplifier A₃ preferablyhaving a gain of one, and whose output is connected to ground through apotentiometer P₁. The intermediate, i.e., sliding terminal ofpotentiometer P₁ is connected through a resistor R₄ to the invertinginput of amplifier A₂, which is also connected to the output thereofthrough a resistor R₅. The values of the resistance of R₃ and thecapacitance of C₃ are selected so that their product (time constant ofthe circuit) is substantially equal to R₁ C₁. Capacitor C₂ can be givena capacitance of any value, for example about of the same magnitude asthat of C₃.

The device operates as follows:

At instant t₀ (FIG. 5) breakers I₁ and I₃ are switched on while breakerI₂ remains in off position. Capacitor C is charged or discharged and thevoltage at its terminals varies from an initial value S₀ to a valuecorresponding to that of the signal, and capacitor C₂ is discharged.

At instant t₁, the breakers I₁ and I₃ are switched off while maintainingin off position the breaker I₂ and the capacitor C memorizes the valueS₁ of the voltage at its terminals, which is available at the output Sof the sample-and-hold unit.

At instant t_(c1), subsequent to t₁, breakers I₁ and I₃ are maintainedin off position, breaker I₂ is switched on and the voltage V_(S) isapplied to the terminals of the passive circuit (C₂, R₃, C₃) resultingin the charge of capacitor C₂. As a consequence of the switching on ofbreaker I₂, a small portion of the output voltage of amplifier A₂ isapplied to the inverting input thereof through an amplifier A₃ andpotentiometer P₁ resulting in a slight change of the output voltagewhich passes from the value S₁ to a slightly lower value S'₁. Thischange is of no practical consequence as far as the holding period (t₁-t_(c1)) is sufficient for the elements following the acquisition chainto exploit the memorized value.

At a later instant t₂, the breaker I₁ is again switched on in order toproceed to a new sampling of the input signal. It is also assumed, tomake more obvious the diaphony phenomenon, that, during the holdingperiod (t₁ -t₂), the input signal has been subjected to an abruptvariation of level and that its amplitude has become very low. Thevoltage V_(c) at terminals of capacitor C (and consequently the voltageV_(s)) varies again substantially up to the value of the input voltageV_(e). The voltage at the terminals of capacitor C₂ will also follow thevariations of voltage V_(s).

At instant t₃ breaker I₁ as well as breaker I₂ is again switched off tomemorize a new sample value. As above-explained, the residual charge ofcapacitor C₁ at instant t₃ is transferred through resistor R₁ tocapacitor C₀ and generates, to the terminals thereof, an error voltage.However, during the same time, the breaker I₃ being in off position, theresidual charge contained at instant t₃ in capacitor C₃ of thecompensation passive circuit, discharges through resistor R₃ intocapacitor C₂, thereby generating an error voltage, a fraction of whichis fed back to the inverting input of amplifier A₂ through amplifier A₃and potentiometer P₁. By a suitable control of potentiometer P₁, thevoltage applied in counter-reaction can be so adjusted that it becomessubstantially equal to the residual voltage introduced at thenon-inverting input of amplifier A₂ and, consequently, nullifies theerror voltage previously appearing at the output of the sample-and-holdunits of a known type.

To summarize, the preceding procedure consists of recreating, on thecompensation passive circuit, the phenomena occurring in the operationof the memorizing capacitor C, i.e., as described with reference to theequivalent circuit of FIG. 3, and to subtract from one another theparasitic or residual voltages occurring, as a consequence of thesephenomena, to the terminals of the capacitor and of the compensationpassive circuit.

The sequence of operations is reproduced from instant t₄ when thebreakers I₁ and I₃ are switched on, and breaker I₂ is maintained in offposition.

The invention can also include control means, as shown in FIG. 4connected by dash lines to breakers I₁, I₂ and I₃, which is conventionalin nature and adapted to alternatively or simultaneously switch on/offthe breakers.

What is claimed is:
 1. In a sample and hold circuit comprising samplingand holding means for receiving signals and temporarily storing saidsignals, and subsequently transmitting said stored signals, saidsampling and holding means comprising capacitor means (C) for receivingand temporarily storing said signals, input means connectable to thecapacitor means (C) for transmitting and charging said capacitor means(C) with said signals, and output means connected to the capacitor means(C) for transmitting the signals stored in the capacitor means (C) forreadout, the improvement which comprises:compensating means forcompensating for parasitic voltages delivered by said sampling andholding means resulting from diaphony between successive samples havingdifferent amplitudes, said compensating means comprising; (a) a passivecompensation circuit including a capacitor (C₂), intermittentlyconnected to the output of said sampling and holding means, andconnected to ground, and said passive compensation circuit adapted toreproduce the operational characteristics of said capacitor means (C),(b) first breaker means (I₂) connected between the output of saidsampling and holding means and said passive compensation circuit forintermittently connecting said passive compensation circuit to theoutput of said sampling and holding means, and second breaker means (I₃)operatively associated with said passive compensation circuit forintermittently short-circuiting said passive compensation circuit, andsaid first and second breaker means adapted for being sequentiallyactuated, and (c) subtracting means operatively associated with saidpassive compensation circuit, and with said sampling and holding means,for subtracting from the voltages stored in capacitor means (C) afraction of a signal stored in capacitor (C₂) to thereby compensate forthe parasitic voltages appearing at the output of said sampling andholding means resulting from diaphony between successive samplestransmitted through said sampling and holding means.
 2. Asample-and-hold circuit according to claim 1, wherein said capacitormeans (C) is selected to be equivalent to a circuit comprising a firstcapacitor (C₀) connected in parallel to a first branched circuitconsisting of a second capacitor (C₁) and a first resistor (R₁)connected in series, and wherein said passive compensation circuitfurther comprises a circuit, connected in parallel to said capacitor(C₂), comprising a second resistor (R₃) and a third capacitor (C₃)connected in series and having a time charge constant through the secondresistor (R₃) substantially equal to that of the second capacitor (C₁)of said first branched circuit of said equivalent circuit.
 3. Asample-and-hold circuit according to claim 2 wherein said sampling andholding means comprises output amplifying means (A₂) operativelyassociated with said capacitor means (C) for amplifying the voltagereceived from the capacitor means (C), and wherein said subtractingcomprises an amplifying circuit (A₃) and means for applying a portion ofthe output voltage of the amplifying circuit (A₃) in inverted form tothe input of said amplifying means (A₂).
 4. A sample-and-hold circuitaccording to claim 3, wherein said sampling and holding means comprisesinput means comprising an amplifier (A₁) having a gain of one, havingits output connected to the capacitor means (C) through a third breakermeans (I₁), and wherein the received signals are applied to the input ofsaid amplifier (A₁).
 5. A sample-and-hold circuit according to claim 2wherein said sampling and holding means comprises input means comprisingthird breaker means (I₁), and wherein said sample-and-hold circuitfurther comprises control means adapted for actuating said first, secondand third breaker means (I₁), (I₂), (I₃).